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| Job Location | Vaughan |
| Education | Not Mentioned |
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| Job Type | Permanent |
Title: ASIC Engineer Location: Markham, ON Duration: 12+ Month TOP 5 REQUIRED SKILLS: 1. 2+ years of ASIC design, verification or related work experience 2. 2+ years experience with architecture and design tools 3. 2+ years experience with scripting tools and programming languages 4. 2+ years experience with design verification methodsOTHER REQUIRED COMPETENCIES* Ability to work legally in Canada * Thorough understanding of Digital design concepts * Strong UVM, System Verilog Skills * Understanding of Bus protocols like AHB/AXI * Perl, Python Scripting experience * Quick understanding of Specs and Standards and developing relevant and thorough test plans * Experience in developing monitors, scoreboards, sequencers and sequences and various aspects of the UVM testbenches * Candidates should be comfortable checking builds, navigating test benches, analyzing coverage, and adding or enabling extra debug * Strong communication skills and works well in a team.TECHNOLOGIES: ASIC IP Verification UVM Development Bus protocols AHB/AXI PERL PythonREQUIRED EDUCATION: Bachelors Degree in Science, Engineering, or related fieldPHYSICAL REQUIREMENTS: 1. Frequently transports between offices, buildings and campuses up to 1/2 mile 2. Frequently transports and installs equipment up to 5 lbs 3. Performs required tasks at various heights (e.g.,standing or sitting) 4. Monitors and utilizes computers and test equipment for more than 6 hours a day 5. Continuous communication which includes the comprehension of information with colleagues, customers and vendors both in person and remotelyJOB DESCRIPTION:As a member of this team, your responsibilities will include: Work closely with design, architects and verification leads to develop the IP verification strategy and testplan. Create verification environment using UVM/System Verilog. Resolve architecture, design or verification problems by applying sound ASIC engineering practices Write tests and regressions to identify any bugs. Develop functional coverage model, assertion checkers and scoreboards. Interpret the results of performance checks and identify issues. Communicate directly with lead on any significant deviations from the Plan of Record for assigned block in a timely manner. Perform RTL code coverage, assertion coverage, functional coverage analysis and gate level simulations Identify opportunities for productivity improvements. Drive and adopt new verification methodologies and flows for efficiency improvements.