Design Engineer (Mid-Senior Level) - Jobs in Greater Vancouver

Job Description

Design Engineer - Mid or Senior levelOnsite preferred in either Portland (USA) or Vancouver (Canada), or remote for the right candidate.Junior to Intermediate experience levels: $80k - $150kSenior to Staff experience levels: $150k - $250kCorporate IntroductionAs a founding premier member of RISC-V International, Andes is the leading supplier and technological innovator in the RISC-V market with a wide range of processor products fulfilling performance/area/power requirements. Andes has perfected the technology of quick and efficient design of custom extensions to its proprietary CPU. With over 10 billion cumulative shipments of SoCs embedded with Andes CPU IP, Andes products have covered audio, Bluetooth, gaming, GPS, machine learning, MCU and more. Our design innovation enables us to quickly adapt to the rapidly evolving demands of RISC-V customers.Founded in 2005, Andes yearly revenue has tripled in size from $10 million in 2017 to $30 million in 2021. Andes was ranked amongquot;100 Fastest-Growing Companies quot; in 2020 by CommonWealth Magazine. Headquartered in Taiwan, Andes is capitalizing on its current growth by branching out its offices to the US and Canada to expand on its current 300 employee workforce. Employees are valued as the key ingredient to the success of the company. They will have an opportunity to create a strong and positive impact on the company, where feedback is encouraged and implemented. RoleThis role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the chance to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.As a member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.Daily activity includes:Communication with peers to discuss technical detailsCompetitive analysis and critique pros and cons, such as the balance of performance, area, powerExplicit CPU hardware design ranging such as fetch units, scheduling, complex vector or floating-point maths, load-store units, coherent memory access or multi-core debug architectureDesign quality analysis including synthesis to assess frequency, area, power qualityProviding technical guidance to junior members of the teamTechnical documentationTechnical RequirementsOver 3 years for Mid level/10 years for Senior level of applicable work experienceBachelor’s or Master’s degree in related engineering fieldStrong communication skillsExperience in bus protocols such as AXI, CHIExperience of ASIC design techniques, pipelines and basic CPU microarchitectureExperience in synthesis, physical layout concepts, static timing analysis, clock domain crossingStrong mastery using Verilog, System VerilogStrong mastery using Unix and scripting languages such as make, shell, perl or pythonAdditional Technical Requirements for Senior Level: Experience of advanced CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug) and assembly languagesDesirable SkillsPatience and good leadership skillsStrong desire to learn and willing to devote extra effort to achieve perfectionStrong team player and possess a positive attitudeExperience or knowledge in verification techniques such as UVM, formal, coverage analysis, bug tracking