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ASIC and FPGA Design Verification Specialist - Jobs in Montréal, QC

Hardent
Job LocationMontréal, QC
EducationNot Mentioned
SalaryNot Disclosed
IndustryNot Mentioned
Functional AreaNot Mentioned
Job TypeFull Time

Job Description

This is a full time position. Please note that work is currently remote-based, due to COVID-19 restrictions.At Hardent, we work with leading tech and semiconductor companies to bring innovative products to market. Our design services and video compression IP cores can be found in some of the world’s most cutting-edge smartphones, AR/VR headsets, medical devices, and automotive systems.As our verification specialist, you will work closely with our customers to define verification plans for complex designs, develop object-oriented transaction-based testbenches and test cases, gather and analyze code coverage and functional coverage metrics for SoC ASIC and FPGA designs, and improve existing HDL-based verification flows.Main Responsibilities

  • Determine customer requirements and develop appropriate verification strategies
  • Define architecture and design verification environments
  • Write test plans and verification documentation
  • Develop verification environments in SystemVerilog/UVM
  • Write test cases
  • Create SystemVerilog assertions and functional coverage models
  • Develop and manage daily regression test flows
  • Perform failure analysis simulations
  • Drive functional and structural coverage closure using industry-leading tools
  • Assist RTL designers with code coverage closure
Requirements
  • Electrical engineering degree or similar
  • 2-10 years’ work experience in a relevant role
  • 2-10 years’ experience in C/C++ language, CSH/BASH/TCL/Perl/Python scripts, makefiles
  • Work experience with functional simulators such as Synopsys VCS, Cadence Xcelium/NCsim, Siemens (Mentor) QuestaSim/ModelSim
  • Knowledge of Verilog, SystemVerilog languages
  • Knowledge of Open Verification Methodology (OVM) or Universal Verification Methodology (UVM)
  • Excellent written and communications skills
  • Strong analytical skills and attention to detail
  • Strong sense of team spirit
Additional Assets
  • Knowledge of Transaction Level Modeling (TLM) with SystemC language
  • Experience with writing common standard Bus Functional Models (BFM)
  • Knowledge of assertion-based verification and formal verification
  • Gate-level verification
  • FPGA and/or ASIC design methodology
  • Experience in RTL design
Employee Benefits
  • Competitive annual salary
  • Brand-new cell phone and generous monthly plan
  • Annual salary adjustment and bonus in line with company performance
  • Access to a family doctor at a private medical clinic
  • Access to a telemedicine service
  • Flexible working hours and a healthy work/life balance
  • Training and professional development opportunities
  • Social activities: team lunches, summer BBQ, annual holiday party, bowling evenings, regular happy hours, karting, etc.
  • And last but not least...cake at the office for your birthday!
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