| Auckland Jobs |
| Canterbury Jobs |
| Northland Jobs |
| Otago Jobs |
| Southland Jobs |
| Tasman Jobs |
| Wellington Jobs |
| West Coast Jobs |
| Auckland Jobs |
| Canterbury Jobs |
| Northland Jobs |
| Otago Jobs |
| Southland Jobs |
| Tasman Jobs |
| Wellington Jobs |
| West Coast Jobs |
| Oil & Gas Jobs |
| Banking Jobs |
| Construction Jobs |
| Top Management Jobs |
| IT - Software Jobs |
| Medical Healthcare Jobs |
| Purchase / Logistics Jobs |
| Sales |
| Ajax Jobs |
| Designing Jobs |
| ASP .NET Jobs |
| Java Jobs |
| MySQL Jobs |
| Sap hr Jobs |
| Software Testing Jobs |
| Html Jobs |
| Job Location | Ontario |
| Education | Not Mentioned |
| Salary | Not Mentioned |
| Industry | Not Mentioned |
| Functional Area | Not Mentioned |
| Job Type | Full Time |
and RequirementsAt Synopsys, we #39;re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we #39;re powering it all with the world #39;s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world #39;s broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications and get differentiated products to market quickly with reduced risk.Physical Design Engineer, Senior StaffSeeking a highly motivated and innovative Physical Design Implementation Engineer for the Test Chip PHY team.Does this sound like a good role for youThe candidate will lead a team of engineers to develop a Test Chip PHY IP for DDR/HBM/UCIe protocols. The position offers an excellent opportunity to work on mixed-signal IPs with focus on digital design.Tasks will include but not be limited to, RTL synthesis, creating floor plans, running Placeamp; Route/CTS flows using Synopsys tools, checking design equivalency, performing Static Timing Analysis and timing closure ECOs, constraints development, static and dynamic IR drop analysis, power estimation, electromigration checks and other verifying the test-chips for DRC/LVS/ERC/PERC checks.Additional tasks will include creation of views necessary for Test Chip tapeout, conducting mock tapeouts and running all required QA checks before release of these views. The candidate will work independently to find solutions to complex design implementation issues and to suggest improvements to the design methodology and design flowsKey Requirements